The present invention relates, to the field of noise analysis models for use in designing digital integrated circuits (xe2x80x9cICsxe2x80x9d). More particularly, the present invention relates to a hierarchical use of a two pole time-gated model of coupling noise of particular utility in analyzing submicron integrated circuit designs to detect or prevent problems due to noise voltages from coupling between various circuit components.
A major factor in the design of high-speed digital circuits is the inevitable parasitic resistances and capacitances that degrade circuit performance. It is known that accurate modeling of digital circuit performance requires that parasitic resistances and capacitances be considered. Software is available from vendors including Cadence Design Systems and Avant!, for extracting the total capacitance, including parasitic capacitances, on nodes of an integrated circuit and for estimating the effect of this capacitance on circuit speed.
Parasitic resistances, capacitances, and inductances are also known to couple noise onto individual nodes of an integrated circuit by coupling signals between adjacent circuit elements. The undesired coupling of signals between adjacent elements is known as crosstalk.
Although digital circuits are inherently resistant to noise, the scaling of supply voltages and metal oxide semiconductor field effect transistor (xe2x80x9cMOSFETxe2x80x9d) threshold voltages has resulted in modern submicron designs having lower noise margins than typical of earlier designs. Most complementary metal oxide semiconductor (xe2x80x9cCMOSxe2x80x9d) circuits continue to have considerable immunity to power supply and substrate noise even at the submicron level. However, the effect of capacitive coupling noise has become a major concern for designers of deep sub-micron circuits.
A good noise detection tool must not only pick out the noise problems on chip, but also be useable on large datasets such as those of ten to twenty million or more transistor integrated circuit designs. Since noise on any given digital circuit is either a problem or it is not, the exact amount of noise induced is not as great a concern to the digital designer, as it is to know whether the induced noise crosses a threshold of potential failure for that net.
The scaling of transistor sizes in digital integrated circuits has also led to the shrinking of wire dimensions. A proportionate scaling (shrinking) of the wire thickness would result in an increasing of wire resistance. To avoid this increase in resistance, the scale factor for the wire thickness has usually been much smaller than the scale factor for horizontal dimensions including wire-to-wire spacing. Further, the space between wires is also reduced by the scaling factor. Hence, the coupling capacitance per unit length between minimally spaced adjacent nodes is greater on modern submicron processes than it is with earlier CMOS digital integrated circuit processes.
Interconnect layers in modern multilayer-metal integrated circuits tend to be designed such that wires on a given layer of metal are generally routed orthogonal to those on an adjacent layer. This orthogonality results in many relatively small parasitic capacitances to circuit elements on the adjacent layers, the noise contribution of these parasitic capacitances is minimal because the contributions of many of these small capacitances tend to cancel each other.
All these factors contribute to a relative increase per unit length in capacitance to neighboring wires and a decrease in the capacitance to the relatively quiet planes above and below the wire. This leads to an increase in the coupling coefficient of a given wire to adjacent wires. In addition, the reduction of the vertical wire dimension, albeit smaller than the scaling factor, and the shrinking of the horizontal wire dimension according to the scale factor, result in an increase in wire resistance that also aggravates the noise situation.
The increased coupling coefficients and wire resistances contribute to much larger noise voltages being induced in deep sub-micron designs than seen in previous generations. These voltages can push digital gates into the amplifying region of their transfer characteristic, turning traditionally noise-rejecting gates into noise amplifying stages. Induced noise voltages can create several different problems on the chip. Of these, designers are most concerned with the detection of faulty logic transitions triggered by noise, especially irrevocable logic transitions, such as the firing of a precharged dynamic gate or corruption of data in a storage element.
Noise voltages and spikes cannot be easily measured on silicon since probing a given net greatly alters its coupling coefficient because of the immense capacitance of the probe. In addition, it is far preferable that parasitic and noise effects be evaluated through pre-tapeout simulation rather than through debugging after wafer fabrication.
Noise problems typically are a function of the data set, the testing frequency and process variations. Large test vector sets are needed to increase the probability that the chip reaches a condition where the effect of coupling noise can be seen during simulation.
A good noise detection methodology can and must ensure that a large and complex chip, such as a modern microprocessor, can be produced and tested without significant delay or cost being added in the noise detection steps.
Noise on any given net in the chip can have one or more of the following effects:
Data loss or metastability in latches, flip-flops or other storage elements. This can result from a noise spike on a clock, reset, set, or latch enable input or from a noise spike on a data input coincident with a clock transition;
Faulty logic transitions, including transitions in dynamic logic gates. Dynamic logic gates may be viewed as a combination of logic and storage elements;
Speed changes leading to setup or hold time violations due to the Miller effect, when the aggressor (the line or lines that induce noise in neighboring lines) and the victim (the line or lines that have noise induced therein) switch in opposite directions;
Substrate bounce due to current injection into the substrate, when voltage excursions due to noise are above or below the supply level; and
Extra power dissipation due to propagated glitches.
It is essential to prevent data loss in latches and flip-flops, and faulty logic transitions in dynamic logic, lest functionality be compromised. The effects on power are typically less significant, while speed changes can be accounted for by guardbanding standard timing tools and by designing the underlying circuits accordingly. The most crucial requirement of a noise detection tool is that it prevents data loss or corruption in storage elements and data corruption due to faulty logic transitions.
The problem of incorrect data stored in storage elements can be subdivided into two categories; frequency dependent noise (wherein a change of clock frequency causes the noise pulse to occur outside the sampling period of the storage element and therefore work correctly at a different frequency); and frequency independent noise (wherein a change of frequency does not shift the noise pulse relative to the sampling period and the error occurs at many frequencies).
To guarantee function, a noise detection strategy should ensure that all frequency independent noise problems are detected such that they may be eliminated and the chip can be guaranteed to work at some frequency.
A tighter criterion is that the strategy should guarantee the chip will work at the target frequency and all lower frequencies. Whatever tool is used, the tool should detect both frequency independent and frequency dependent noise problems that may cause functional failure at the target frequency.
A third, stricter, criterion that may be applied in a conservative design, is to prevent all faulty logic transitions induced by coupled noise.
To verify large devices, of the order of a million transistors or more, it is necessary that circuit modeling be done with a tool that is faster and less memory intensive than those which construct full-circuit matrix equations, as does the circuit simulator SPICE. SPICE is well known to those of skill in the art.
A noise detection tool should also allow for sensitivity analysis on the circuit parameters. This enables designers to run xe2x80x9cwhat ifxe2x80x9d analysis on suspect wires during design and redesign. For example, analysis may be repeated for a process minimum and a process maximum of metal line-to-line or layer-to-layer spacing, or for a typical, versus a minimum, enhancement device threshold.
It is also desirable that errors in a coupling-noise detection tool err on the side of pessimism rather than on the side of optimism, i.e., it is better to use a conservative model. This is because, while pessimistic or conservative analysis may result in some degree of extra labor in design of an integrated circuit, the resulting design can be guaranteed to work. In contrast, an optimistic analysis may result in undetected problems remaining in a design.
Most integrated circuit designs are subjected to repeated analysis to detect design rule violations and circuit speed problems during the design process. It is also known that typical large integrated circuit layouts have large numbers of parasitic capacitances. Extraction of all capacitances and resistances, and their reduction for modeling, of a large integrated circuit therefore requires considerable computer time. It is desirable that this computer time be minimized.
In accordance with the principles of the invention, a high capacity noise analysis tool is created for analyzing potential noise coupling in submicron integrated circuit designs. One embodiment of the invention uses a two-pole model of coupling. This embodiment is a program product operational on a digital computer permitting it to analyze large numbers of aggressor and victim wires.
According to the principles of the invention, the speed of analysis is enhanced by combining multiple aggressors into single aggressors for analysis, and by performing a hierarchical analysis.
According to the invention, the speed of analysis is optionally further boosted through topology-based parameter estimation for the two-pole coupling model. In this embodiment, topology-based parameter estimates are used with the two-pole model of coupling to generate a list of wires that have potential for noise problems. This list may be examined by the user, or may be reexamined by the tool of the invention with more precisely calculated circuit parameters.